The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for selectively floating a dummy bit line based on the operation mode of the cell array.
As shown in FIG. 1, a typical DRAM semiconductor memory device includes bit lines BL and word lines WL. The bit lines and the word lines WL intersect to form the pattern shown in FIG. 1. In a DRAM semiconductor memory device cell arrays include a plurality of unit cells. Each unit cell consists of a transistor and a capacitor. A bit line sense amplifier SA senses and amplifies respective signals of a bit line pair BL and /BL.
The following describes the operation of the semiconductor memory device when in active mode: the word line WL becomes a high driving voltage VPP level; the bit line pair BL and /BL gradually varies from a precharge voltage VLBP level to power voltage and ground voltage levels respectively to increase the potential difference therebetween; and a dummy bit line DBL connected to a dummy cell at a peripheral region of the cell array maintains the precharge voltage VLBP level even when in the active mode.
When in active mode, a short bridge caused by process defects can be formed by self aligned contact (SAC) between the word line WL and the dummy bit line DBL in the dummy cell. When this occurs, the high driving voltage VPP level of the word line WL is lowered by the precharge voltage VBLP level of the dummy bit line DBL.
Referring to the timing diagram of FIG. 2, the VPP level voltage of the word line WL is abnormally swung between the VPP and VBLP voltage levels when in active mode since the word line WL forms a short with the bit line BL due to the SAC failure.
As such, when the voltage of the word line WL is dropped to less than the VPP level voltage, data transmission to the cell array is weakened during read and write operations.
Therefore, the conventional semiconductor memory device has a problem in that the DRAM operation properties are lowered by the above described defect.